1. Field of the Invention
This invention relates to a transistor and method for making a transistor with a built-in voltage clamp. More specifically the invention relates to a power switching transistor, such as a DMOS or insulated gate bipolar transistor, which has a built-in region which serves as a voltage clamp surrounded by the active portion of the transistor and which breaks down at a lower voltage than do the other junctions in the transistor.
2. Description of the Prior Art
DMOSFET's (double diffused metal oxide silicon field effect transistors) and IGBT s (insulated gate bipolar transistors) are well-known in the art. A typical example of one cell of a DMOSFET transistor is shown in FIG. 1A. The DMOSFET is a field effect transistor as shown having source regions 10a and 10b formed respectively in body 26 regions 12a, 12b which are in turn formed in an epitaxial layer 14 (i.e., a drain region) grown on a substrate 16. A gate 18 is formed over an insulating layer 20 on the principal surface 22 of the epitaxial layer 14. A drain contact 24 is attached to the backside of the substrate 16. A gate contact 28 and source/body contact 30 are also provided. FIG. 1A thus shows a conventional power DMOSFET.
An insulated gate bipolar transistor (IGBT) has a somewhat similar structure as the DMOSFET of FIG. 1A, except that for the IGBT substrate region 16 would be a P+ region (i.e., of opposite conductivity type to that of the expitaxial layer 14). The IGBT in effect is internally a field effect transistor (FET) with its source connected to the collector of a wide base bipolar transistor and its drain connected to the base of the wide base bipolar transistor. The emitter terminal of the wide base transistor then is referred to as the collector terminal of the IGBT; the collector terminal of the wide base transistor is referred to as the IGBT emitter terminal, and the FET gate terminal is the IGBT gate terminal. Thus for the IGBT corresponding to the structure of FIG. 1A, the epitaxial layer 14 is the base region. The body regions 12a, 12b are shorted to the IGBT emitter regions 10a, 10b. The substrate 16 (which is of P+type) is the IGBT collector region.
Therefore, the chief structural difference between an insulated gate bipolar transistor and a DMOSFET is in the conductivity type of the substrate. In an insulated gate bipolar transistor the epitaxial region is an open base region, meaning there is no electrical contact of that region to any external structures. This structure is also referred to as a floating base region.
Prior art power transistors typically include many (e.g., ten thousand) cells of the kind shown in FIG. 1A, each cell being identical. As shown in FIG. 1B in a top view, for a DMOSFET 32 each cell 34, 36, 38, 40 is a polygon such as a square which includes a central P+source region 34a, 36a, 38a, 40a formed in and surrounded by an N+ body region 34b, 36b, 38b, 40b. Each cell 34, 36, 38, 40 is in turn surrounded by a polycrystalline silicon (i.e., polysilicon) conductive gate region 44 which is the conductive gate region for the entire transistor.
In another well known prior art cell structure (not shown), open linear cells are provided. Each cell typically includes a linear P+ source region formed in between linear N+ body regions. Between adjacent cells a polysilicon gate region is provided.
It is known that in devices such as shown in FIG. 1A, a diffused region such as collector region 12a (which is typically delineated by means of a window in a photo-etched oxide mask) is parallel plane in shape, with the exception of part of the region defined by the edge of the window in the oxide. At the edge of the window in the oxide, owing to diffusion effects, the region takes on a cylindrical shape in cross section. Thus the space charge lines at the window edge are distorted, resulting in an electric field that is different from the parallel plane electric field structure. Thus for a particular applied voltage, the peak electric field is higher for the cylindrical junction than for the parallel plane junction. Thus the breakdown voltage is lower for the cylindrical junction than for the parallel plane, and so breakdown tends to occur at the cylindrical junction.
It is also known in the art that at the curved region where two cylindrical junctions meet, such as at the corner of a rectangular shaped diffused region, a so-called spherical junction is formed. The electrical breakdown of a spherical junction typically occurs at an even lower breakdown voltage than is experienced with a cylindrical junction. This is because extremely small curvature radii are encountered at such sharp corner regions associated with a diffusion area which is masked through a rectangular window.
FIG. 1C shows that the breakdown voltage of a spherical junction is lower than the breakdown voltage of a cylindrical junction. The breakdown voltage of the spherical junction is typically about 60% of that of a cylindrical junction, where the radius of the junction divided by the thickness of the lightly-doped semiconductor is approximately 0.1. In FIG. 1C, r.sub.j is the radius of the junction, and W' is the thickness of the lightly-doped semiconductor. BV/BV.sub.pp is the breakdown voltage relative to that of a parallel plane.
The prior art power DMOS and insulated gate bipolar transistor devices typically have spherical or at best cylindrical shaped PN junctions. As indicated above, the spherical junctions typically break down at lower voltage values than do the cylindrical junctions. As also indicated above, a cylindrical junction breaks down at a lower voltage value than does a planar junction.
Thus the prior art power transistor devices as described above typically experience electrical breakdown at the corners of their diffused regions. This electrical breakdown is undesirable, because it can lead to heating at the breakdown region due to excessive current flowing through that spot. This is especially a problem because power transistors are intended to be subjected to high currents, and so this heating can catastrophically destroy the transistor.
It is therefore desirable to have a transistor device for use in power switching which does not break down at the active part of the transistor.
In U.S. Pat. No. 4,779,123, issued Oct. 18, 1988, incorporated herein by reference, Bencuya et al. disclose an improved insulated gate bipolar transistor having a high conductivity collector well surrounding the active portion of the transistor. This collector well prevents undesirable transistor latching. Latching is a phenomenon whereby a semiconductor structure "latches" into a self-perpetuating state of bipolar conduction, which cannot be turned off by removing the voltage bias on the gate to stop FET mode conduction. However, Bencuya et al. do not disclose any method of dealing with the breakdown problem.